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| EM39LV010 1M Bits (128Kx8) Flash Memory SPECIFICATION General Description The EM39LV010 is a 1M bits Flash memory organized as 128K x 8 bits. The EM39LV010 uses 2.7-3.6V power supply for Program and Erase. Featuring high performance Flash memory technology, the EM39LV010 provides a typical Byte-Program time of 11 sec and a typical Sector-Erase time of 40 ms. The device uses Toggle Bit or Data# Polling to detect the completion of the Program or Erase operation. To protect against inadvertent write, the device has on-chip hardware and software data protection schemes. The device offers typical 100,000 cycles endurance and a greater than 10 years data retention. The EM39LV010 conforms to JEDEC standard pin outs for x8 memories. The EM39LV010 is offered in package types of 32-lead PLCC, 32-pin TSOP, 48-ball FBGA, and known good dice (KGD). For KGD, please contact ELAN Microelectronics or its representatives for detailed information (see Appendix at the bottom of this specification for Ordering Information). The EM39LV010 devices are developed for applications that require memories with convenient and economical updating of program, data or configuration, e.g., Networking cards, Card Readers, Graphic cards, Digital TV, MP3, Wireless Phones, etc. Features Single Power Supply Full voltage range from 2.7 to 3.6 volts for both read and write operations Sector-Erase Capability Uniform 4Kbyte sectors Read Access Time Access time: 45, 70 and 90 ns Power Consumption Active current: 15 mA (Typical) Standby current: 1 A (Typical) Erase/Program Features Sector-Erase Time: 40 ms (Typical) Chip-Erase Time: 40 ms (Typical) Byte-Program Time: 11s (Typical) Chip Rewrite Time: 1.5 seconds (Typical) Automatic Write Timing Internal VPP Generation End-of-Program or End-of-Erase Detection Data# Polling Toggle Bit CMOS I/O Compatibility JEDEC Standard Pin-out and software command sets compatible with single-power supply Flash memory High Reliability Endurance cycles: 100K (Typical) Data retention: 10 years Package Option 32-lead PLCC 32-pin TSOP 48-pin FBGA This specification is subject to change without further notice. (04.09.2004 V1.0) Page 1 of 23 EM39LV010 1M Bits (128Kx8) Flash Memory SPECIFICATION Functional Block Diagram Flash M em ory Array X-Decoder Mem ory Address Address Buffer & Latches Y-Decoder CE# OE# W E# Control Logic I/O Buffers and Data Latches DQ7-DQ0 Figure 0a: Functional Block Diagram Pin Assignments PLCC A12 A15 A16 NC VDD W E# NC 4 3 2 1 32 31 30 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 29 28 27 26 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 32-Lead PLCC Top View 25 24 23 22 13 21 14 15 16 17 18 19 20 DQ1 DQ2 VSS DQ3DQ4 DQ5 DQ6 Figure 0b: 32-lead PLCC Pin Assignments This specification is subject to change without further notice. (04.09.2004 V1.0) Page 2 of 23 EM39LV010 1M Bits (128Kx8) Flash Memory SPECIFICATION TSOP A11 A9 A8 A13 A14 NC W E# VDD NC A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 V SS DQ2 DQ1 DQ0 A0 A1 A2 A3 Standard TSOP Figure 0c: TSOP Pin Assignments FBGA FB G A Top View , B alls Facing D ow n A14 A13 A 15 A16 A17 NC NC V SS A9 A8 A11 A 12 A1 9 A10 DQ6 DQ7 W E# NC NC NC DQ5 NC VDD DQ4 NC NC NC NC DQ2 DQ 3 VDD NC A7 A18 A6 A5 DQ0 NC NC DQ1 A3 A4 A2 A1 A0 C E# O E# V SS Figure 0d: FBGA Pin Assignments This specification is subject to change without further notice. (04.09.2004 V1.0) Page 3 of 23 EM39LV010 1M Bits (128Kx8) Flash Memory SPECIFICATION Pin Description Pin Name A0-A19 DQ7-DQ0 CE# OE# WE# VDD VSS NC 17 addresses Data inputs/outputs Chip enable Output enable Write enable 2.7-3.6 volt single power supply Device ground Pin not connected internally Function Table 1: Pin Description Device Operation The EM39LV010 uses Commands to initiate the memory operation functions. The Commands are written to the device by asserting WE# Low while keeping CE# Low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. Read The Read operation of the EM39LV010 is controlled by CE# and OE#. Both have to be Low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read Cycle Timing Diagram in Figure 1 for further details. Byte Program The EM39LV010 is programmed on a byte-by-byte basis. Before programming, the sector where the byte is located; must be erased completely. The Program operation is accomplished in three steps: The first step is a three-byte load sequence for Software Data Protection. The second step is to load byte address and byte data. During the Byte Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last; and the data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 16 s. See Figures 2 and 3 for WE# and CE# controlled Program operation timing diagrams respectively and Figure 12 for flowchart. This specification is subject to change without further notice. (04.09.2004 V1.0) Page 4 of 23 EM39LV010 1M Bits (128Kx8) Flash Memory SPECIFICATION During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During internal Program operation, the host is free to perform additional tasks. Any command issued during the internal Program operation is ignored. EM39LV010 Device Operation Operation Read Program Erase Standby Write Inhibit Write Inhibit Software Mode Product Identification CE# VIL VIL VIL VIH X X VIL OE# VIL VIH VIH X VIL X VIL WE# VIH VIL VIL X X VIH VIH DQ DOUT DIN X * Address AIN AIN Sector address, XXH for Chip-Erase X X X See Table 3 High Z High Z/DOUT High Z/DOUT * X can be VIL or VIH, but no other value. Table 2: EM39LV010 Device Operation Write Command/Command Sequence The EM39LV010 provides two software methods to detect the completion of a Program or Erase cycle in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. The actual completion of the write operation is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent such spurious rejection, when an erroneous result occurs, the software routine should include an additional two times loop to read the accessed location. If both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid. Chip Erase The EM39LV010 provides Chip-Erase feature, which allows the entire memory array to be erased to logic "1" state. The Chip-Erase operation is initiated by executing a six-byte command sequence with Chip-Erase command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid reads are Toggle Bit and Data# Polling. See Table 3 for the command sequence, Figure 6 for timing diagram, and Figure 15 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. This specification is subject to change without further notice. (04.09.2004 V1.0) Page 5 of 23 EM39LV010 1M Bits (128Kx8) Flash Memory SPECIFICATION Sector Erase The EM39LV010 offers Sector-Erase mode. The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The sector architecture is based on uniform sector size of 4 KByte. The Sector-Erase operation is initiated by executing a six-byte command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The sector address is latched on the falling edge of the sixth WE# pulse, while the command (30H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase operation can be determined by using either Data# Polling or Toggle Bit method. See Figures 7 for timing waveforms. Any commands issued during the Sector Erase operation are ignored. Data# Polling (DQ7) When the EM39LV010 is in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce the true data. Note that even though DQ7 may have valid data immediately following the completion of an internal Program operation, the remaining data outputs may still be invalid (valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 s). During internal Erase operation, any attempt to read DQ7 will produce a "0". Once the internal Erase operation is completed, DQ7 will produce a "1". The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-Erase or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 4 for Data# Polling timing diagram and Figure 13 for a flowchart. Toggle Bit (DQ6) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating 1s and 0s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-Erase or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 5 for Toggle Bit timing diagram and Figure 13 for a flowchart. Data Protection The EM39LV010 provides both hardware and software features to protect the data from inadvertent write. This specification is subject to change without further notice. (04.09.2004 V1.0) Page 6 of 23 EM39LV010 1M Bits (128Kx8) Flash Memory SPECIFICATION Hardware Data Protection Noise/Glitch Protection: VDD Power Up/Down Detection: Write Inhibit Mode: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle. The Write operation is inhibited when VDD is less than 1.5V. Forcing OE# Low, CE# High, or WE# High will inhibit the Write operation. This prevents inadvertent write during power-up or power-down. Software Data Protection (SDP) The EM39LV010 provides the JEDEC approved Software Data Protection (SDP) scheme for Program and Erase operations. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, especially during the system power-up or power-down transition. Any Erase operation requires the inclusion of six-byte sequence. See Table 3 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode within TRC. This specification is subject to change without further notice. (04.09.2004 V1.0) Page 7 of 23 EM39LV010 1M Bits (128Kx8) Flash Memory SPECIFICATION Software Command Sequence Command Sequence Byte Program Sector Erase Chip Erase Software ID 4,6 Entry Manufacture ID Manufacture ID Manufacture ID Device ID Software ID 5 Exit /CFI Exit Software ID 5 Exit /CFI Exit 1st Bus Write Cycle Addr 1 2nd Bus Write Cycle Addr 1 3rd Bus Write Cycle Addr 1 4th Bus Write Cycle Addr BA 2 1 5th Bus Write Cycle Addr 1 6th Bus Write Cycle Addr 1 Data AAH AAH AAH AAH AAH AAH AAH AAH F0H AAH Data 55H 55H 55H 55H 55H 55H 55H 55H Data A0H 80H 80H 90H 90H 90H 90H 90H Data Data AAH AAH Data Data 5555H 5555H 5555H 5555H 5555H 5555H 5555H 5555H XXH 5555H 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 5555H 5555H 5555H 5555H 5555H 5555H 5555H 5555H 5555H 5555H 2AAAH 2AAAH 55H 55H SAX3 5555H 30H 10H 0000H 0003H 0040H 0001H 7FH 7FH 1FH A8H 2AAAH 55H 5555H F0H Notes: 1. Address format A15-A0 (Hex), Address A16 can be VIL or VIH, but no other value, for the Command sequence. 2. BA = Program byte address. 3. SAX for Sector-Erase; uses A16-A12 address lines. 4. The device does not remain in Software Product ID mode if powered down. 5. Both Software ID Exit operations are equivalent. 6. Refer to Figure 9 for more information. Table 3: Software Command Sequence This specification is subject to change without further notice. (04.09.2004 V1.0) Page 8 of 23 EM39LV010 1M Bits (128Kx8) Flash Memory SPECIFICATION Absolute Maximum Ratings NOTE Applied conditions greater than those listed under these ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this specification, are not implied. Exposure to absolute maximum stress rating conditions may affect device reliability. Temperature Under Bias ............................................................ -55C to 125C Storage Temperature .................................................................. -65C to 150C D.C. Voltage on Any Pin to Ground Potential ............................. -0.5 V to VDD+0.5V Transient Voltage (<20ns) on Any Pin to Ground Potential .......... -2.0V to VDD +2.0V Voltage on A9 Pin to Ground Potential ......................................... -0.5 V to 13.2V Package Power Dissipation Capability (Ta=25C)........................ 1.0W Surface Mount Lead Soldering Temperature (3 Seconds)............ 240C Output Short Circuit Current * ...................................................... 50mA * Output shorted for no more than one second. No more than one output shorted at a time. Operating Range Model Name EM39LV010 Ambient Temperature 0C to +70C VDD 2.7~3.6V Table 4: Operating Range AC Conditions of Test Input Rise/Fall Time ..................................................................... 5ns Output Load ................................................................................. CL=30pF for 45Rns Output Load ................................................................................. CL=100pF for 70ns/90ns See Figures 10 and 11 This specification is subject to change without further notice. (04.09.2004 V1.0) Page 9 of 23 EM39LV010 1M Bits (128Kx8) Flash Memory SPECIFICATION DC CHARACTERISTICS (CMOS Compatible) Parameter Description Power Supply Current IDD Read Program and Erase ISB ILI ILO VIL VIH VIHC VOL VOH Standby VDD Current Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Input High Voltage (CMOS) Output Low Voltage Output High Voltage Test Conditions Address Input =VIL/VIH, at f=1/TRC Min, VDD=VDD Max CE#=OE#=VIL, WE#=VIH, all I/Os open CE#=WE#=VIL, OE#=VIH, CE#=VIHC, VDD=VDD Max VIN=GND to VDD, VDD=VDD Max VOUT=GND to VDD, VDD=VDD Max VDD=VDD Min VDD=VDD Max VDD=VDD Max IOL=100A, VDD=VDD Min IOH=-100A, VDD=VDD Min Min Max Unit 20 30 15 1 10 0.8 0.7 VDD VDD-0.3 0.2 VDD-0.2 mA mA A A A V V V V V Table 5: DC Characteristics (Cmos Compatible) Recommended System Power-up Timing Parameter TPU-READ* TPU-WRITE* Description Power-up to Read Operation Power-up to Program/Erase Operation Min 100 100 Unit s s * This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. Table 6: Recommended System Power-up Timing Capacitance (Ta=25C, f=1Mhz, other pins open) Parameter CI/O* CIN* Description I/O Pin Capacitance Input Capacitance Test Conditons VI/O=0V VIN=0V Max 12pF 6pF * This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. Table 7: Capacitance (Ta=25C, f=1Mhz, Other Pins Open) Reliability Characteristics Symbol NEND* TDR* ILTH* Parameter Endurance Data Retention Latch Up Min Specification 10,000 10 100+IDD Unit Cycles Years mA Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard 78 * This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. Table 8: Reliability Characteristics Page 10 of 23 This specification is subject to change without further notice. (04.09.2004 V1.0) EM39LV010 1M Bits (128Kx8) Flash Memory SPECIFICATION AC Characteristics Read Cycle Timing Parameters Symbol TRC TCE TAA TOE TCLZ* TOLZ* TCHZ* TOHZ* TOH* Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE# Low to Active Output OE# Low to Active Output CE# High to High-Z Output OE# High to High-Z Output Output Hold from Address Change 45REC Min 45 45 45 30 0 0 15 15 0 70REC Min 70 70 70 35 0 0 25 25 0 90REC Min 90 90 90 45 0 0 30 30 0 Max Max Max Unit ns ns ns ns ns ns ns ns ns * This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. Table 9a: Read Cycle Timing Parameters 45EC Min 45 45 45 30 0 0 15 15 0 0 0 0 25 25 0 Symbol TRC TCE TAA TOE TCLZ* TOLZ* TCHZ* TOHZ* TOH* Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE# Low to Active Output OE# Low to Active Output CE# High to High-Z Output OE# High to High-Z Output Output Hold from Address Change 70EC Min 70 70 70 35 0 0 90EC Min 90 90 90 45 Max Max Max Unit ns ns ns ns ns ns 30 30 ns ns ns * This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. Table 9b: Read Cycle Timing Parameters This specification is subject to change without further notice. (04.09.2004 V1.0) Page 11 of 23 EM39LV010 1M Bits (128Kx8) Flash Memory SPECIFICATION Program/Erase Cycle Timing Parameter Symbol TBP TAS TAH TCS TCH TOES TOEH TCP TWP TWPH* TCPH* TDS TDH* TIDA* TSE TSCE Parameter Byte-Program Time Address Setup Time Address Hold Time WE# and CE# Setup Time WE# and CE# Hold Time OE# High Setup Time OE# High Hold Time CE# Pulse Width WE# Pulse Width WE# Pulse Width High CE# Pulse Width High Data Setup Time Data Hold Time Software ID Access and Exit Time Sector Erase Chip Erase Min 0 30 0 0 0 10 40 40 30 30 40 0 Max 16 Unit s ns ns ns ns ns ns ns ns ns ns ns ns 150 30 60 ns ms ms * This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. Table 10: Program/Erase Cycle Timing Parameter Timing Diagrams Read Cycle Timing Diagram TRC A16~A0 CE# TCE TAA OE# TOE TOHZ VIH W E# TOLZ TCLZ TOH Data Valid TCHZ Data Valid HIGH-Z DQ7-0 HIGH-Z Figure 1: Read Cycle Timing Diagram Page 12 of 23 This specification is subject to change without further notice. (04.09.2004 V1.0) EM39LV010 1M Bits (128Kx8) Flash Memory SPECIFICATION WE# Controlled Program Cycle Timing Diagram Internal Program Operation Starts TBP A19~A0 5555 TAH W E# TW P TW PH TAS OE# TDS 2AAA 5555 ADDR TDH CE# TCS DQ7-0 AA SW 0 55 SW 1 TCH A0 SW 2 DATA Byte (ADDR/DATA) Figure 2: WE# Controlled Program Cycle Timing Diagram CE# Controlled Program Cycle Timing Diagram Internal Program Operation Starts TBP A16~A0 5555 TAH CE# TCP TCPH TAS OE# TDS 2AAA 5555 ADDR TDH W E# TCS DQ7-0 AA SW 0 55 SW 1 TCH A0 SW 2 DATA Byte (ADDR/DATA) Figure 3: CE# Controlled Program Cycle Timing Diagram This specification is subject to change without further notice. (04.09.2004 V1.0) Page 13 of 23 EM39LV010 1M Bits (128Kx8) Flash Memory SPECIFICATION Data# Polling Timing Diagram A16~A0 TCE CE# TOEH OE# TOE W E# TOES DQ7 DATA DATA# DATA# DATA# Figure 4: Data# Polling Timing Diagram Toggle Bit Timing Diagram A16~A0 TCE CE# TOEH OE# W E# DQ6 Two Read Cycles W ith Sam e Outputs TOE TOES Figure 5: Toggle Bit Timing Diagram This specification is subject to change without further notice. (04.09.2004 V1.0) Page 14 of 23 EM39LV010 1M Bits (128Kx8) Flash Memory SPECIFICATION WE# Controlled Chip-Erase Timing Diagram Six-Byte Code For Chip-Erase TSCE 5555 A16~A0 CE# OE# 5555 2AAA 5555 5555 2AAA TW P W E# AA SW 0 55 SW 1 80 SW 2 AA SW 3 55 SW 4 10 SW 5 DQ7-0 Note: This device also supports CE# controlled Chip-Erase operation. The W E#and CE# signals are interchageable as long as m inimum tim ings are m et. (See Table 10) Figure 6: WE# Controlled Chip-Erase Timing Diagram WE# Controlled Sector-Erase Timing Diagram Six-Byte Code For Sector-Erase TSE SAX A16~A0 CE# OE# 5555 2AAA 5555 5555 2AAA TW P W E# AA SW 0 55 SW 1 80 SW 2 AA SW 3 55 SW 4 30 SW 5 DQ7-0 Note: This device also supports CE# controlled Sector-Erase operation. The W E#and CE# signals are interchageable as long as m inimum tim ings are m et. (See Table 10) SAX=Sector Address X can be VIL or VIH, but no other value. Figure 7: WE# Controlled Sector-Erase Timing Diagram This specification is subject to change without further notice. (04.09.2004 V1.0) Page 15 of 23 EM39LV010 1M Bits (128Kx8) Flash Memory SPECIFICATION Software ID Entry and Read Three-Byte Sequence For Software ID Entry Address A14-0 CE# OE# TW P W E# TW PH DQ7-0 AA SW 0 55 SW 1 90 SW 2 TIDA TAA 7F 7F 1F A8 5555 2AAA 5555 0000H 0003H 0040H 0001H Figure 8: Software ID Entry and Read Software ID Exit and Reset Three-Byte Sequence For Software ID Exit and Reset Address A14-0 DQ7-0 CE# OE# TW P W E# SW 0 TW PH SW 1 SW 2 5555 AA 2AAA 55 5555 F0 TIDA Figure 9: Software ID Exit and Reset This specification is subject to change without further notice. (04.09.2004 V1.0) Page 16 of 23 EM39LV010 1M Bits (128Kx8) Flash Memory SPECIFICATION AC Input/Output Reference Waveforms VIHT Input VILT AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and VILT(0.1 VDD) for a logic "0". Measurement reference points for inputs and outpputs are VIT(0.5 VDD) and VOT(0.5 VDD). Input rise and fall times(10% - 90% ) are <5ns VIT Reference Points VOT Output Note: VIT = Vinput Test VOT = Voutput Test VIHT = Vinput HIGH Test VILT = Vinput LOW Test Figure 10: AC Input/Output Reference Waveforms A Test Load Example TO TESTER TO DUT CL Figure 11: A Test Load Example This specification is subject to change without further notice. (04.09.2004 V1.0) Page 17 of 23 EM39LV010 1M Bits (128Kx8) Flash Memory SPECIFICATION Byte-Program Algorithm Start Load Data: AAH Address: 5555H Load Data: 55H Address: 2AAAH Load Data: A0H Address: 5555H Load Byte Address/Byte Data W ait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Com pleted Figure 12: Byte-Program Algorithm This specification is subject to change without further notice. (04.09.2004 V1.0) Page 18 of 23 EM39LV010 1M Bits (128Kx8) Flash Memory SPECIFICATION Flow Charts Wait Options Internal Tim er Progrm /Erase Initiated Toggle Bit Progrm/Erase Initiated Data# Polling Progrm /Erase Initiated W ait TBP, TSCE, TSE or TBE Read Byte Read DQ7 Progrm /Erase Com pleted Read Sam e Byte Is DQ7=true data? Yes No Does DQ6 m atch? Yes Progrm/Erase Com pleted No Progrm /Erase Com pleted Figure 13: Wait Options This specification is subject to change without further notice. (04.09.2004 V1.0) Page 19 of 23 EM39LV010 1M Bits (128Kx8) Flash Memory SPECIFICATION Software ID Command Flowcharts Internal Tim er Progrm /Erase Initiated Toggle Bit Progrm/Erase Initiated Data# Polling Progrm /Erase Initiated W ait TBP, TSCE, TSE or TBE Read Byte Read DQ7 Progrm /Erase Com pleted Read Sam e Byte Is DQ7=true data? Yes No Does DQ6 m atch? Yes Progrm/Erase Com pleted X can be VIL or VIH, but no other value. No Progrm /Erase Com pleted Figure 14: Software ID Command Flowcharts This specification is subject to change without further notice. (04.09.2004 V1.0) Page 20 of 23 EM39LV010 1M Bits (128Kx8) Flash Memory SPECIFICATION Erase Command Sequence Software ID Entry Comm and Sequence Load Data: AAH Address: 5555H Software ID Exit Comm and Sequence Load Data: AAH Address: 5555H Load Data: F0H Address: XXH Load Data: 55H Address: 2AAAH Load Data: 55H Address: 2AAAH W ait TIDA Load Data: 90H Address: 5555H Load Data: F0H Address: 5555H Return to Norm al Operation W ait TIDA W ait TIDA Read Software ID Return to Norm al Operation X can be VIL or VIH, but no other value. Figure 15: Erase Command Sequence This specification is subject to change without further notice. (04.09.2004 V1.0) Page 21 of 23 EM39LV010 1M Bits (128Kx8) Flash Memory SPECIFICATION Appendix ORDERING INFORMATION (Standard Products) The order number is defined by a combination of the following elements. EM39LV010 -70 M Description Package Type (1 digit) M Y L H D 45R 70 90 ** **R = TSOP (Type 1, die up, 8mm x 14mm) = FBGA (0.8mm pitch, 6mm x 8mm) = 32-pin PLCC = Chip Form = Known Good Dice (for wafer dice sell) = 45ns = 70ns = 90ns = VDD = 2.7-3.6V = VDD=3.0-3.6V Speed Option (2-3 digits) Device Number/Description EM39LV010 1 Megabit (128K x 8-Bit) Flash Memory 2.7-3.6 Volt only Read, Program, and Erase This specification is subject to change without further notice. (04.09.2004 V1.0) Page 22 of 23 EM39LV010 1M Bits (128Kx8) Flash Memory SPECIFICATION ORDERING INFORMATION (Non-Standard Products) For Known Good Dice (KGD), please contact ELAN Microelectronics at the following contact information or its representatives. ELAN MICROELECTRONICS CORPORATION Headquarters: No. 12, Innovation Road 1 Science-based Industrial Park Hsinchu, Taiwan, R.O.C. 30077 Tel: +886 3 563-9977 Fax: +886 3 563-9966 http://www.emc.com.tw Hong Kong: Elan (HK) Microelectronics Corporation, Ltd. Rm. 1005B, 10/F Empire Centre 68 Mody Road, Tsimshatsui Kowloon , HONG KONG Tel: +852 2723-3376 Fax: +852 2723-7780 elanhk@emc.com.hk USA: Elan Information Technology Group 1821 Saratoga Ave., Suite 250 Saratoga, CA 95070 USA Tel: +1 408 366-8223 Fax: +1 408 366-8220 Europe: Elan Microelectronics Corp. (Europe) Dubendorfstrasse 4 8051 Zurich, SWITZERLAND Tel: +41 43 299-4060 Fax: +41 43 299-4079 http://www.elan-europe.com Shenzhen: Elan (Shenzhen) Microelectronics Corp., Ltd. SSMEC Bldg., 3F, Gaoxin S. Ave. Shenzhen Hi-Tech Industrial Park Shenzhen, Guandong, CHINA Tel: +86 755 2601-0565 Fax: +86 755 2601-0500 Shanghai: Elan Electronics (Shanghai) Corporation, Ltd. 23/Bldg. #115 Lane 572, Bibo Road Zhangjiang Hi-Tech Park Shanghai, CHINA Tel: +86 021 5080-3866 Fax: +86 021 5080-4600 This specification is subject to change without further notice. (04.09.2004 V1.0) Page 23 of 23 |
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